A storage controller includes a plurality of pipeline stages configured to process data. A system clock signal is received that has a system frequency and at least one performance metric is determined for one or more pipeline stages of the plurality of pipeline stages. A first clock signal is generated having a first frequency for operation of a first pipeline stage of the plurality of pipeline stages. Based at least in part on the at least one determined performance metric, a second clock signal is generated having a second frequency for operation of a second pipeline stage of the plurality of pipeline stages. The second frequency is less than the system frequency and may also differ from the first frequency.