A method of generating a layout diagram for an integrated circuit. The method includes arranging a plurality of cells in the layout diagram. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.