Invention Grant
- Patent Title: Memory sub-system with a virtualized bus and internal logic to perform a machine learning operation
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Application No.: US16601386Application Date: 2019-10-14
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Publication No.: US11769076B2Publication Date: 2023-09-26
- Inventor: Amit Gattani , Poorna Kale
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06N20/00
- IPC: G06N20/00 ; G06F13/16 ; G06F3/06 ; G06N3/08

Abstract:
A memory component includes a memory region to store a machine learning model and input data and another memory region to store host data from a host system. A controller can be coupled to the memory component and can include in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and a decoder can receive the additional data from the bus and can transmit the additional data to the other memory region or the in-memory logic of the controller based on a characteristic of the additional data.
Public/Granted literature
- US20210110297A1 MEMORY SUB-SYSTEM WITH A VIRTUALIZED BUS AND INTERNAL LOGIC TO PERFORM A MACHINE LEARNING OPERATION Public/Granted day:2021-04-15
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