Invention Grant
- Patent Title: Dual trace thickness for single layer routing
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Application No.: US16017671Application Date: 2018-06-25
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Publication No.: US11769719B2Publication Date: 2023-09-26
- Inventor: Jonathan Rosch , Wei-Lun Jen , Cheng Xu , Liwei Cheng , Andrew Brown , Yikang Deng
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt. P.C.
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/18 ; H01L23/498 ; H01L21/48 ; H05K1/02

Abstract:
Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.
Public/Granted literature
- US20190393143A1 DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING Public/Granted day:2019-12-26
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