Invention Grant
- Patent Title: Programmable chopping architecture to reduce offset in an analog front end
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Application No.: US17901654Application Date: 2022-09-01
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Publication No.: US11770109B2Publication Date: 2023-09-26
- Inventor: Erhan Hancioglu , Eashwar Thiagarajan , Eric Mann , Harold Kutz , Vaibhav Ramamoorthy , Rajiv Singh , Amsby Richardson, Jr.
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H03F1/02
- IPC: H03F1/02 ; H03F3/38 ; H03F3/387 ; H03M3/00

Abstract:
An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.
Public/Granted literature
- US20230055860A1 PROGRAMMABLE CHOPPING ARCHITECTURE TO REDUCE OFFSET IN AN ANALOG FRONT END Public/Granted day:2023-02-23
Information query
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