Invention Grant
- Patent Title: 3D ferroelectric memory
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Application No.: US17854701Application Date: 2022-06-30
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Publication No.: US11770935B2Publication Date: 2023-09-26
- Inventor: Sheng-Chih Lai , Chung-Te Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- The original application number of the division: US16903545 2020.06.17
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H10B51/20 ; H01L29/78 ; H01L21/28 ; H01L29/66 ; H10B51/30 ; H10B51/40

Abstract:
Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.
Public/Granted literature
- US20220336498A1 3D FERROELECTRIC MEMORY Public/Granted day:2022-10-20
Information query
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