Invention Grant
- Patent Title: Methods and apparatus to simulate metastability for circuit design verification
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Application No.: US18072842Application Date: 2022-12-01
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Publication No.: US11775718B2Publication Date: 2023-10-03
- Inventor: Sudhakar Surendran , Venkatraman Ramakrishnan
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Mandy Barsilai Fernandez; Frank D. Cimino
- Priority: IN 2141007687 2021.02.24
- Main IPC: G06F30/3312
- IPC: G06F30/3312 ; G06F30/327 ; G06F30/367 ; G06F30/398 ; G06F119/02 ; G06F117/04

Abstract:
Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.
Public/Granted literature
- US20230088503A1 METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN VERIFICATION Public/Granted day:2023-03-23
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