Invention Grant
- Patent Title: Systems and methods for obfuscating a circuit design
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Application No.: US17493576Application Date: 2021-10-04
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Publication No.: US11775722B2Publication Date: 2023-10-03
- Inventor: Bertrand Irissou , John M. Hughes , Lucio Lanza , Mohamed K. Kassem , Michael S. Wishart , Rajeev Srivastava , Risto Bell , Robert Timothy Edwards , Sherif Eid , Greg P. Shaurette
- Applicant: efabless corporation
- Applicant Address: US CA San Jose
- Assignee: efabless corporation
- Current Assignee: efabless corporation
- Current Assignee Address: US CA San Jose
- Agency: Penilla IP, APC
- Main IPC: G06F30/39
- IPC: G06F30/39 ; G06F30/30 ; G06F30/33 ; G06F30/367 ; G06F30/392 ; G06F30/398 ; G06F30/3323 ; H01L23/00 ; G06F119/18

Abstract:
Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.
Public/Granted literature
- US20220027544A1 SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN Public/Granted day:2022-01-27
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