- Patent Title: Static random-access memory (SRAM) compute in-memory integration
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Application No.: US16672722Application Date: 2019-11-04
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Publication No.: US11776608B2Publication Date: 2023-10-03
- Inventor: Xia Li , Jianguo Yao , Bin Yang
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G11C11/40 ; G06F9/30 ; G11C11/54 ; G11C11/413 ; H03K19/21

Abstract:
Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.
Public/Granted literature
- US20210134343A1 STATIC RANDOM-ACCESS MEMORY (SRAM) COMPUTE IN-MEMORY INTEGRATION Public/Granted day:2021-05-06
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