An application processor includes a memory interface and a memory controller. The memory interface is connected to a semiconductor memory device through first data input/output (I/O) pads and second data I/O pads. The memory controller exchanges data with the semiconductor memory device by controlling the memory interface. The memory interface includes a training circuit to perform duty training of first data signals and second data signals by adjusting a duty of each of the first data signals with respect to a first reference voltage and adjusting a duty of each of the second data signals with respect to a second reference voltage.