Invention Grant
- Patent Title: Method for preparing semiconductor device structure with fine patterns at different levels
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Application No.: US17511042Application Date: 2021-10-26
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Publication No.: US11776813B2Publication Date: 2023-10-03
- Inventor: Cheng-Hsiang Fan
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US16811824 2020.03.06
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/308 ; H01L21/762 ; H01L21/768 ; H01L21/764 ; H01L21/311

Abstract:
The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.
Information query
IPC分类: