Invention Grant
- Patent Title: Semiconductor arrangement and method of making
-
Application No.: US17536345Application Date: 2021-11-29
-
Publication No.: US11776845B2Publication Date: 2023-10-03
- Inventor: Hsi-Wen Tien , Wei-Hao Liao , Pin-Ren Dai , Chih Wei Lu , Chung-Ju Lee
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsinchu
- Agency: COOPER LEGAL GROUP, LLC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L21/3213 ; H01L21/311

Abstract:
A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
Public/Granted literature
- US20220084875A1 SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING Public/Granted day:2022-03-17
Information query
IPC分类: