Invention Grant
- Patent Title: FPGA device forming network-on-chip by using silicon connection layer
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Application No.: US17294985Application Date: 2020-12-30
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Publication No.: US11776915B2Publication Date: 2023-10-03
- Inventor: Jicong Fan , Yanfeng Xu , Yueer Shan , Hua Yan , Yanfei Zhang
- Applicant: WUXI ESIONTECH CO., LTD.
- Applicant Address: CN Jiangsu
- Assignee: WUXI ESIONTECH CO., LTD.
- Current Assignee: WUXI ESIONTECH CO., LTD.
- Current Assignee Address: CN Jiangsu
- Agency: Hamre, Schumann, Mueller & Larson, P.C.
- Priority: CN 2010620258.7 2020.07.01
- International Application: PCT/CN2020/141194 2020.12.30
- International Announcement: WO2022/001064A 2022.01.06
- Date entered country: 2021-05-18
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/065 ; H01L23/00 ; H01L23/535 ; G06F30/394 ; G06F30/39 ; H03K19/17736 ; G06F15/78 ; G06F30/347 ; H10B80/00

Abstract:
The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.
Public/Granted literature
- US20220216156A1 FPGA DEVICE FORMING NETWORK-ON-CHIP BY USING SILICON CONNECTION LAYER Public/Granted day:2022-07-07
Information query
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