Invention Grant
- Patent Title: Integrated circuit filler and method thereof
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Application No.: US17659645Application Date: 2022-04-18
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Publication No.: US11776948B2Publication Date: 2023-10-03
- Inventor: Tseng Chin Lo , Molly Chang , Ya-Wen Tseng , Chih-Ting Sun , Zi-Kuan Li , Bo-Sen Chang , Geng-He Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US15484628 2017.04.11
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L21/66 ; G06F30/392 ; H10B10/00 ; H01L21/027 ; H01L21/8234

Abstract:
Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
Public/Granted literature
- US20220246600A1 INTEGRATED CIRCUIT FILLER AND METHOD THEREOF Public/Granted day:2022-08-04
Information query
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