Invention Grant
- Patent Title: Semiconductor apparatus having a silicide between two devices
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Application No.: US17844573Application Date: 2022-06-20
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Publication No.: US11776954B2Publication Date: 2023-10-03
- Inventor: Mark I. Gardner , H. Jim Fulford
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- The original application number of the division: US17113736 2020.12.07
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L21/8238

Abstract:
Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.
Public/Granted literature
- US20220320079A1 Method of Architecture Design for Enhanced 3D Device Performance Public/Granted day:2022-10-06
Information query
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