Invention Grant
- Patent Title: Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices
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Application No.: US17648690Application Date: 2022-01-24
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Publication No.: US11777017B2Publication Date: 2023-10-03
- Inventor: Te-Yang Lai , Chun-Yen Peng , Sai-Hooi Yeong , Chi On Chui
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US16825874 2020.03.20
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/51 ; H01L21/02 ; H01L29/78

Abstract:
Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.
Public/Granted literature
- US20220149182A1 NEGATIVE-CAPACITANCE AND FERROELECTRIC FIELD-EFFECT TRANSISTOR (NCFET AND FE-FET) DEVICES Public/Granted day:2022-05-12
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