Invention Grant
- Patent Title: Memory subword driver layout
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Application No.: US17171906Application Date: 2021-02-09
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Publication No.: US11778813B2Publication Date: 2023-10-03
- Inventor: Masahiro Yokomichi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C11/408
- IPC: G11C11/408 ; H10B12/00 ; G11C5/06 ; H01L29/417

Abstract:
Semiconductor devices including active regions and gate electrodes are disclosed. An example semiconductor device according to the disclosure includes a gate electrode extending in a first direction, and first and second active regions extending in a second direction. The gate electrode has a side extending in the first direction. The first active region includes: a first center portion having a first width in the first direction; and a first end portion disposed at a first end of the first center portion, and having a second width in the first direction that is greater than the first width. The second active region includes: a second center portion having a third width in the first direction. The gate electrode overlaps along the side with portions of the first end portion and the second center portion.
Public/Granted literature
- US20220254788A1 MEMORY SUBWORD DRIVER LAYOUT Public/Granted day:2022-08-11
Information query
IPC分类: