Invention Grant
- Patent Title: Cache architecture for a storage device
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Application No.: US17865341Application Date: 2022-07-14
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Publication No.: US11782854B2Publication Date: 2023-10-10
- Inventor: Dionisio Minopoli , Daniele Balluchi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F12/10 ; G06F12/121 ; G11C16/04

Abstract:
The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.
Public/Granted literature
- US11741027B2 Cache architecture for a storage device Public/Granted day:2023-08-29
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