A system includes a serial peripheral interface (SPI) buffer configured at an initial position. A low voltage differential signaling (LVDS) transceiver is configured above the SPI buffer. A capacitor couples the LVDS transceiver with the SPI buffer. The SPI buffer does not interfere with signals from the LVDS transceiver. The LVDS transceiver does not interfere with signals from the SPI buffer. An input/output (I/O) module receives a signal from the LVDS transceiver or the SPI buffer.