A process condition measurement wafer assembly is disclosed. In embodiments, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and interposed between the top substrate and bottom substrate. In another embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom substrate and the top substrate. In embodiments, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and diffuse voltage potentials across the bottom substrate and the top substrate.