Invention Grant
- Patent Title: Isolation gap filling process for embedded dram using spacer material
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Application No.: US16260632Application Date: 2019-01-29
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Publication No.: US11784088B2Publication Date: 2023-10-10
- Inventor: Chieh-Jen Ku , Bernhard Sell , Pei-Hua Wang , Harish Ganapathy , Leonard C. Pipes
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H10B12/00
- IPC: H10B12/00 ; H01L21/762

Abstract:
Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.
Public/Granted literature
- US20200243376A1 ISOLATION GAP FILLING PROCESS FOR EMBEDDED DRAM USING SPACER MATERIAL Public/Granted day:2020-07-30
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