Invention Grant
- Patent Title: Inter-level connection for multi-layer structures
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Application No.: US18084292Application Date: 2022-12-19
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Publication No.: US11784183B2Publication Date: 2023-10-10
- Inventor: Yi-Tang Lin , Clement Hsingjen Wann , Neng-Kuo Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- The original application number of the division: US14080940 2013.11.15
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L23/522 ; H01L27/088

Abstract:
Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
Public/Granted literature
- US20230123873A1 INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES Public/Granted day:2023-04-20
Information query
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