Invention Grant
- Patent Title: Semiconductor gate-all-around device having an anti-punch-through (APT) layer including carbon
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Application No.: US17097945Application Date: 2020-11-13
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Publication No.: US11784226B2Publication Date: 2023-10-10
- Inventor: Jhon Jhy Liaw
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/78 ; H01L27/092 ; H01L29/786 ; H01L29/06 ; H01L29/423 ; H01L21/8238 ; H01L29/66

Abstract:
A metal-oxide semiconductor field effect transistor (MOSFET) includes a substrate and a well over the substrate, the well including dopants of a first conductivity-type. The well includes an anti-punch-through (APT) layer at an upper section of the well, the APT layer including the dopants of the first conductivity-type and further including carbon. The MOSFET further includes a source feature and a drain feature adjacent the APT layer, being of a second conductivity-type opposite to the first conductivity-type. The MOSFET further includes multiple channel layers over the APT layer and connecting the source feature to the drain feature, wherein the multiple channel layers are vertically stacked one over another. The MOSFET further includes a gate wrapping around each of the channel layers, such as in a gate-all-around device, wherein a first portion of the gate is disposed between a bottommost one of the channel layers and the APT layer.
Public/Granted literature
- US20220157941A1 Semiconductor Gate-All-Around Device Public/Granted day:2022-05-19
Information query
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