Invention Grant
- Patent Title: Method for manufacturing wiring board
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Application No.: US17672067Application Date: 2022-02-15
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Publication No.: US11785721B2Publication Date: 2023-10-10
- Inventor: Haruki Kondoh , Rentaro Mori , Keiji Kuroda , Kazuaki Okamoto , Akira Kato , Jyunya Murai , Hiroshi Yanagimoto , Kenji Nakamura , Tomoya Okazaki
- Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
- Applicant Address: JP Toyota
- Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
- Current Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
- Current Assignee Address: JP Toyota
- Agency: Sughrue Mion, PLLC
- Priority: JP 21025668 2021.02.19
- Main IPC: H05K3/10
- IPC: H05K3/10 ; C25D5/02 ; C25D7/00 ; H05K3/18

Abstract:
First, a patterned substrate including an insulating substrate, a conductive seed layer, and an insulating layer is prepared. The seed layer is disposed on the insulating substrate, and consists of a first part having a predetermined pattern corresponding to the wiring pattern and a second part as a part other than the first part. The insulating layer is disposed on the second part of the seed layer. Subsequently, a metal layer having a thickness larger than a thickness of the insulating layer is formed on the first part of the seed layer. Here, a voltage is applied between an anode and the seed layer while a resin film containing a metal ion-containing solution is disposed between the patterned substrate and the anode and the resin film and the seed layer are brought into pressure contact. Subsequently, the insulating layer and the second part of the seed layer are removed.
Public/Granted literature
- US20220272847A1 METHOD FOR MANUFACTURING WIRING BOARD Public/Granted day:2022-08-25
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