Invention Grant
- Patent Title: Gate-all-around semiconductor device with dielectric-all-around capacitor and method for fabricating the same
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Application No.: US17839837Application Date: 2022-06-14
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Publication No.: US11785760B2Publication Date: 2023-10-10
- Inventor: Liang-Pin Chou
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US17136812 2020.12.29
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L21/02 ; H01L29/66 ; H01L29/786 ; H01L49/02 ; H01L29/423 ; H01L29/06 ; H10B12/00

Abstract:
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first stack structure positioned on a first substrate, a first impurity region and a second impurity region respectively positioned on opposing sides of the first stack structure and operatively associated with the first stack structure, a second stack structure positioned above the first stack structure with a middle insulation layer interposed therebetween, and a third impurity region positioned on one side of the second stack structure and electrically coupled to the second impurity region. The first stack structure includes a plurality of first semiconductor layers and a plurality of gate assemblies alternatively arranged. The plurality of gate assemblies includes a gate dielectric and a gate electrode. The second stack structure includes a plurality of second semiconductor layers and a plurality of capacitor sub-units alternatively arranged. The plurality of capacitor sub-units including a capacitor dielectric and a capacitor electrode.
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Information query
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