Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.