Invention Grant
- Patent Title: Sequential voltage ramp-down of access lines of non-volatile memory device
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Application No.: US17888041Application Date: 2022-08-15
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Publication No.: US11790991B2Publication Date: 2023-10-17
- Inventor: Albert Fayrushin , Augusto Benvenuti , Akira Goda , Luca Laurin , Haitao Liu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- The original application number of the division: US16183414 2018.11.07
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/08 ; G11C16/16 ; G11C16/24 ; G11C16/26

Abstract:
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.
Public/Granted literature
- US20220392533A1 SEQUENTIAL VOLTAGE RAMP-DOWN OF ACCESS LINES OF NON-VOLATILE MEMORY DEVICE Public/Granted day:2022-12-08
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