Invention Grant
- Patent Title: Chip package structure
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Application No.: US17554475Application Date: 2021-12-17
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Publication No.: US11791301B2Publication Date: 2023-10-17
- Inventor: Shin-Puu Jeng , Shuo-Mao Chen , Feng-Cheng Hsu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- The original application number of the division: US15708456 2017.09.19
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L21/56 ; H01L25/10 ; H01L25/00 ; H01L21/683 ; H01L23/31 ; H01L23/29 ; H01L21/78

Abstract:
A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump connected between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the first redistribution structure. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive bump connected between the second chip and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the first redistribution structure.
Public/Granted literature
- US20220108967A1 CHIP PACKAGE STRUCTURE Public/Granted day:2022-04-07
Information query
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