- Patent Title: Self-aligned vertical integration of three-terminal memory devices
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Application No.: US17283645Application Date: 2019-10-22
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Publication No.: US11792987B2Publication Date: 2023-10-17
- Inventor: Thorsten Lill , Meihua Shen , John Hoang , Hui-Jung Wu , Gereng Gunawan , Yang Pan
- Applicant: LAM RESEARCH CORPORATION
- Applicant Address: US CA Fremont
- Assignee: LAM RESEARCH CORPORATION
- Current Assignee: LAM RESEARCH CORPORATION
- Current Assignee Address: US CA Fremont
- International Application: PCT/US2019/057418 2019.10.22
- International Announcement: WO2020/086566A 2020.04.30
- Date entered country: 2021-04-08
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H10B41/10 ; H10B41/27 ; H10B43/10 ; H10B51/10 ; H10B51/20

Abstract:
A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.
Public/Granted literature
- US20210391355A1 SELF-ALIGNED VERTICAL INTEGRATION OF THREE-TERMINAL MEMORY DEVICES Public/Granted day:2021-12-16
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