Invention Grant
- Patent Title: Efficient placement of memory
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Application No.: US17763813Application Date: 2020-10-15
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Publication No.: US11798599B2Publication Date: 2023-10-24
- Inventor: Jung Soo Park
- Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
- Applicant Address: US TX Spring
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Spring
- Agency: Brooks, Cameron & Huebsch, PLLC
- Priority: KR 20190128364 2019.10.16
- International Application: PCT/US2020/055724 2020.10.15
- International Announcement: WO2021/076721A 2021.04.22
- Date entered country: 2022-03-25
- Main IPC: G11C5/02
- IPC: G11C5/02 ; G11C7/10 ; G11C8/12

Abstract:
An electronic apparatus includes a circuit board, a memory chip mounted on the circuit board, a memory controller to control an operation of the memory chip, a conductive pattern including a first control line to connect from a first terminal of the memory chip to a first terminal of the memory chip and a second control line to connect from a second terminal of the memory controller to a second terminal of the memory chip, and a capacitive element to provide a termination voltage. The first control line is connected to the capacitive element and the second control line is not connected to the capacitive element.
Public/Granted literature
- US20220358969A1 EFFICIENT PLACEMENT OF MEMORY Public/Granted day:2022-11-10
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