Invention Grant
- Patent Title: Wafer-scale integration with alternative technology wafer processes that can be folded into three-dimensional packaging
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Application No.: US16669735Application Date: 2019-10-31
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Publication No.: US11798901B1Publication Date: 2023-10-24
- Inventor: Ian J. Forster
- Applicant: AVERY DENNISON RETAIL INFORMATION SERVICES, LLC
- Applicant Address: US OH Mentor
- Assignee: Avery Dennison Retail Information Services LLC
- Current Assignee: Avery Dennison Retail Information Services LLC
- Current Assignee Address: US OH Mentor
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L27/00

Abstract:
Semiconductor wafer devices are formed of a wafer or a portion of a wafer. The wafer or wafer portion includes a plurality of functional blocks, one of which comprises an energy source and another which takes some other form, such as digital logic, data storage, a communication module, a display, a display driver, or a sensor. A functional block may be formed as part of processing of the wafer or may comprise a post-processing element. The functional blocks combine to provide an operational system having a plurality of functions. The wafer may be formed of an amorphous material, allowing the device to have a three-dimensional, non-planar structure, such as a cuboidal or tubular structure. If the device comprises only a portion of a wafer, a plurality of devices may be formed from a single wafer, with each portion being removed from the remainder of the wafer to define a device.
Information query
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