Invention Grant
- Patent Title: Semiconductor device and chip singulation method
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Application No.: US17399869Application Date: 2021-08-11
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Publication No.: US11798986B2Publication Date: 2023-10-24
- Inventor: Yoshihiro Matsushima , Yoshihiko Kawakami , Shinya Oda , Takeshi Harada
- Applicant: NUVOTON TECHNOLOGY CORPORATION JAPAN
- Applicant Address: JP Kyoto
- Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
- Current Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
- Current Assignee Address: JP Kyoto
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/78 ; H01L29/78

Abstract:
A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 μm; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 μm. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-μm square region located at least 13 μm inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.
Public/Granted literature
- US20220013633A1 SEMICONDUCTOR DEVICE AND CHIP SINGULATION METHOD Public/Granted day:2022-01-13
Information query
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