Invention Grant
- Patent Title: Method and apparatus for data caching
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Application No.: US17640276Application Date: 2019-11-28
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Publication No.: US11803475B2Publication Date: 2023-10-31
- Inventor: Haiwei Liu , Gang Dong , Hongbin Yang , Yaqian Zhao , Rengang Li , Hongzhi Shi
- Applicant: Inspur Electronic Information Industry Co., Ltd.
- Applicant Address: CN Shandong
- Assignee: INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD.
- Current Assignee: INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD.
- Current Assignee Address: CN Jinan
- Agency: DINSMORE & SHOHL LLP
- Priority: CN 1910827022.8 2019.09.03
- International Application: PCT/CN2019/121571 2019.11.28
- International Announcement: WO2021/042594A 2021.03.11
- Date entered country: 2022-03-03
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0855 ; G06F12/0897

Abstract:
The present invention provides a method and apparatus for data caching. The method comprises: output matrixes are acquired one by one, a plurality of acquired output matrixes are written alternately into two queue sets of a first cache unit according to a sequence in which the output matrixes are acquired, and the output matrixes stored line by line in a first cache unit are written into a second cache unit one by one, according to the sequence in which the output matrixes are written into the second cache unit, valid data of each output matrix of the second cache unit is determined one by one according to preset parameters, and the valid data of each output matrix is written into a third cache unit, and the valid data of the output matrixes stored in the third cache unit are configured to be sequentially written into a memory according to a sequence in which the valid data are written into the third cache unit. In the present solution, the output matrixes are cached by using cache units with the writing speed matching with the computing speed of a processor, and the output matrixes are completely written into a memory one by one according to a sequence of generation time. Therefore, the present invention may solve the problem that the computing speed of the processor does not match with the writing speed of the memory.
Public/Granted literature
- US20220342824A1 METHOD AND APPARATUS FOR DATA CACHING Public/Granted day:2022-10-27
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