Invention Grant
- Patent Title: Instruction prefetch mechanism
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Application No.: US17210867Application Date: 2021-03-24
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Publication No.: US11803476B2Publication Date: 2023-10-31
- Inventor: Vasileios Porpodas , Guei-Yuan Lueh , Subramaniam Maiyuran , Wei-Yu Chen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: JAFFERY WATSON MENDONSA & HAMILTON LLP
- Main IPC: G06F12/0862
- IPC: G06F12/0862 ; G06F12/0875 ; G06F9/30 ; G06F8/41

Abstract:
An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.
Public/Granted literature
- US20210279177A1 INSTRUCTION PREFETCH MECHANISM Public/Granted day:2021-09-09
Information query
IPC分类: