Invention Grant
- Patent Title: Method of fabrication thereof a multi-level vertical memory device including inter-level channel connector
-
Application No.: US17462736Application Date: 2021-08-31
-
Publication No.: US11805643B2Publication Date: 2023-10-31
- Inventor: Ruo Fang Zhang , Enbo Wang , Haohao Yang , Qianbing Xu , Yushi Hu , Qian Tao
- Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee Address: CN Wuhan
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- The original application number of the division: US16367305 2019.03.28
- Main IPC: H10B41/27
- IPC: H10B41/27 ; H10B41/35

Abstract:
Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.
Public/Granted literature
- US20210398999A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF Public/Granted day:2021-12-23
Information query