A port controller circuit is configured to control power transfer on a power path between a first terminal and a second terminal. The controller circuit includes first and second transistors connected in series between the first terminal and the second terminal, a control terminal of the first transistor receiving a first gate voltage and a control terminal of the second transistor receiving a second gate voltage. A first gate voltage control circuit generates the first gate voltage driving the control terminal of the first transistor and regulates the first gate voltage to keep the first transistor turned on. In response to the first gate voltage control circuit regulating the first gate voltage to a voltage value less than a first voltage level, the first gate voltage control circuit asserts a first signal to indicate a fault condition at the first transistor.