Invention Grant
- Patent Title: Apparatus for low power ternary logic circuit
-
Application No.: US17175570Application Date: 2021-02-12
-
Publication No.: US11817858B2Publication Date: 2023-11-14
- Inventor: Seokhyeong Kang , Sunghye Park , SungYun Lee , Sunmean Kim
- Applicant: POSTECH Research and Business Development Foundation
- Applicant Address: KR Pohang-si
- Assignee: POSTECH Research and Business Development Foundation
- Current Assignee: POSTECH Research and Business Development Foundation
- Current Assignee Address: KR Pohang-si
- Agency: Morgan, Lewis & Bockius LLP
- Priority: KR 20200129024 2020.10.06
- Main IPC: H03K19/00
- IPC: H03K19/00 ; H10K10/46 ; G06F119/06

Abstract:
A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.
Public/Granted literature
- US20220109444A1 APPARATUS FOR LOW POWER TERNARY LOGIC CIRCUIT Public/Granted day:2022-04-07
Information query