A microcontroller powered by a power management integrated circuit (PMIC) includes a plurality of cores. A first core of the microcontroller can be configured to implement a system power transient management component. One or more other or second cores of the microcontroller can be configured to implement one or more applications. The system power transient management component implemented by the first core can be configured to dynamically identify an expected load transient event to occur in the microcontroller, determine power control data to optimize a response to the identified expected load transient event, the power control data comprising a power control mode and associated parameters, and provide the power control data to the power management integrated circuit (PMIC).