Invention Grant
- Patent Title: Methods and circuits for reducing clock jitter
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Application No.: US17719974Application Date: 2022-04-13
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Publication No.: US11831323B2Publication Date: 2023-11-28
- Inventor: Marcus Van Ierssel , Prabhnoor Singh Kainth , Nanyan Wang
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark Whittenberger, Esq.
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H03L7/107 ; H03L7/093 ; H03L7/08 ; H04L7/02

Abstract:
A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.
Public/Granted literature
- US20220329247A1 Methods and Circuits for Reducing Clock Jitter Public/Granted day:2022-10-13
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