Invention Grant
- Patent Title: Semiconductor device and error detection methods
-
Application No.: US17738542Application Date: 2022-05-06
-
Publication No.: US11831337B2Publication Date: 2023-11-28
- Inventor: Takashi Ishibashi , Hiroyuki Hashimoto
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP 21108192 2021.06.29
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/15

Abstract:
A semiconductor device includes a syndrome generation circuit configured to generate a syndrome code based on data and an error correction code corresponding to the data, an error determination circuit configured to detect a 1-bit error in the data based on the syndrome code, and multi-bit error detection circuit configured to determine whether the data detected to have 1-bit error includes a multi-bit error by using an error address of the data detected to have 1-bit error and an error syndrome code of the data detected to have 1-bit error.
Public/Granted literature
- US20220416813A1 SEMICONDUCTOR DEVICE AND ERROR DETECTION METHODS Public/Granted day:2022-12-29
Information query
IPC分类: