Invention Grant
- Patent Title: Semiconductor chip stack with locking through vias
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Application No.: US16936629Application Date: 2020-07-23
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Publication No.: US11837527B2Publication Date: 2023-12-05
- Inventor: Travis Boraten
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/525 ; H01L25/18 ; H01L23/00 ; H01L25/00

Abstract:
Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.
Public/Granted literature
- US20220028757A1 SEMICONDUCTOR CHIP STACK WITH LOCKING THROUGH VIAS Public/Granted day:2022-01-27
Information query
IPC分类: