Invention Grant
- Patent Title: Method of making 3D isolation
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Application No.: US17094947Application Date: 2020-11-11
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Publication No.: US11842919B2Publication Date: 2023-12-12
- Inventor: Mark I. Gardner , H. Jim Fulford
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L29/775
- IPC: H01L29/775 ; H01L21/762 ; H01L29/78 ; H01L29/66 ; H01L21/8238 ; H01L27/092

Abstract:
A method of microfabrication is provided. An initial stack of layers is formed over a semiconductor layer. The initial stack of layers can include a plurality of substacks separated from each other by one or more transition layers. One or more of the substacks include a sacrificial gate layer sandwiched between two first dielectric layers. Openings can be formed in the initial stack of layers so that the semiconductor layer is uncovered. The openings can be filled with vertical channel structures, where each vertical channel structure extends through a respective substack. The initial stack can be divided into separate stacks that include the vertical channel structures surrounded by the substacks and the transition layers. The one or more transition layers can be removed from the separate stacks to uncover transition points between neighboring vertical channel structures. Isolation structures can be formed at the transition points.
Public/Granted literature
- US20210391207A1 METHOD OF MAKING 3D ISOLATION Public/Granted day:2021-12-16
Information query
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