Invention Grant
- Patent Title: Backside power rail structure and methods of forming same
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Application No.: US17682701Application Date: 2022-02-28
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Publication No.: US11842965B2Publication Date: 2023-12-12
- Inventor: Kuo-Cheng Chiang , Shi Ning Ju , Chih-Chao Chou , Wen-Ting Lan , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L29/786 ; H01L21/02 ; H01L21/285 ; H01L21/306 ; H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/45 ; H01L29/66

Abstract:
Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
Public/Granted literature
- US20220181259A1 Backside Power Rail Structure and Methods of Forming Same Public/Granted day:2022-06-09
Information query
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