Invention Grant
- Patent Title: Integration of p-channel and n-channel E-FET III-V devices without parasitic channels
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Application No.: US17751849Application Date: 2022-05-24
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Publication No.: US11843047B2Publication Date: 2023-12-12
- Inventor: Man-Ho Kwan , Fu-Wei Yao , Chun Lin Tsai , Jiun-Lei Jerry Yu , Ting-Fu Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- The original application number of the division: US16589440 2019.10.01
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/06 ; H01L29/423 ; H01L29/778 ; H01L29/66
Abstract:
In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.
Public/Granted literature
- US20220285540A1 INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITHOUT PARASITIC CHANNELS Public/Granted day:2022-09-08
Information query
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