An apparatus includes a plurality of pixels, a comparator configured to compare an output signal of each of the plurality of pixels with a reference signal, and a counter of K bits (K is a natural number) configured to operate in parallel with operation of the comparator. The apparatus converts the output signal of each of the plurality of pixels into a digital signal using an output of the comparator and an output of the counter. The apparatus includes an addition unit configured to add a plurality of the digital signals. The addition unit includes a serial binary adder of M bits (M is a natural number less than K).