Packet processing apparatus and packet processing method
Abstract:
A packet processing apparatus includes a memory, a processor, a first gate, and a second gate. The memory stores a plurality of allocation patterns for allocating an upstream or downstream of a link direction for each subframe within a predetermined period. The processor obtains a periodicity pattern of a high-priority packet for each of time slots within the subframe. The first gate opens and closes, for each of the time slots within the subframe, output of the high-priority packet. The second gate opens and closes, for each of the time slots within the subframe, output of a low-priority packet. The processor sets gate states of the first gate and the second gate for a predetermined time slot within the subframe in the same link direction as the periodicity pattern to a priority state in which the high-priority packet is preferentially output according to the periodicity pattern.
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