Structure for multiple sense amplifiers of memory device
Abstract:
A memory device is provided. The memory device includes several sense amplifiers and at least one reference cell. Each of the sense amplifiers has a first terminal and a second terminal. The first terminals of the sense amplifiers are coupled to a memory cell block, and the second terminals of the sense amplifiers are coupled together to transmit a read current. The at least one reference cell transmits the read current to a ground terminal. The at least one reference cell has a decreased resistance value when a number N of the sense amplifiers increases.
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