Invention Grant
- Patent Title: Spacer etching process for integrated circuit design
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Application No.: US16882063Application Date: 2020-05-22
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Publication No.: US11854820B2Publication Date: 2023-12-26
- Inventor: Ru-Gun Liu , Cheng-Hsiung Tsai , Chung-Ju Lee , Chih-Ming Lai , Chia-Ying Lee , Jyu-Horng Shieh , Ken-Hsien Hsieh , Ming-Feng Shieh , Shau-Lin Shue , Shih-Ming Chang , Tien-I Bao , Tsai-Sheng Gau
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US15357203 2016.11.21
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/033 ; H01L21/311 ; H01L21/768 ; H01L21/02 ; H01L21/027 ; H01L21/3105 ; H01L21/8234

Abstract:
A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.
Public/Granted literature
- US20200286738A1 Spacer Etching Process For Integrated Circuit Design Public/Granted day:2020-09-10
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