Invention Grant
- Patent Title: Anti-oxidation layer to prevent dielectric loss from planarization process
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Application No.: US17337803Application Date: 2021-06-03
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Publication No.: US11854822B2Publication Date: 2023-12-26
- Inventor: Zhen Yu Guan , Hsun-Chung Kuang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/02 ; H01L21/768

Abstract:
In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
Public/Granted literature
- US20220293429A1 ANTI-OXIDATION LAYER TO PREVENT DIELECTRIC LOSS FROM PLANARIZATION PROCESS Public/Granted day:2022-09-15
Information query
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