Invention Grant
- Patent Title: TLC data programming with hybrid parity
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Application No.: US17202163Application Date: 2021-03-15
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Publication No.: US11861195B2Publication Date: 2024-01-02
- Inventor: Sergey Anatolievich Gorobets , Alan D. Bennett , Liam Parker , Yuval Shohet , Michelle Martin
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: PATTERSON + SHERIDAN, LLP
- Agent Steven H. VerSteeg
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10

Abstract:
The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.
Public/Granted literature
- US20220291838A1 TLC Data Programming With Hybrid Parity Public/Granted day:2022-09-15
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